#[repr(C)]
pub struct StandardDetails { pub cardbus_cis_ptr: u32, pub subsystem: SubsystemId, pub exp_rom_base_addr: u32, pub cap_ptr: u8, pub irq_line: u8, pub min_grant: u8, pub max_latency: u8, /* private fields */ }
Expand description

A header describing a standard PCI device (not a bridge).

Much of the documentation for this struct’s fields was copied from the OSDev Wiki.

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§cardbus_cis_ptr: u32

Points to the Card Information Structure and is used by devices that share silicon between CardBus and PCI.

§subsystem: SubsystemId§exp_rom_base_addr: u32

Expansion ROM base address.

§cap_ptr: u8

Points (i.e. an offset into this function’s configuration space) to a linked list of new capabilities implemented by the device. Used if bit 4 of the status register (Capabilities List bit) is set to 1. The bottom two bits are reserved and should be masked before the Pointer is used to access the Configuration Space.

§irq_line: u8

Specifies which input of the system interrupt controllers the device’s interrupt pin is connected to and is implemented by any device that makes use of an interrupt pin.

For the x86 architectures, this register corresponds to the PIC IRQ numbers 0-15 (and not I/O APIC IRQ numbers) and a value of 0xFF defines no connection.

§min_grant: u8

A read-only register that specifies the burst period length, in 1/4 microsecond units, that the device needs (assuming a 33 MHz clock rate).

§max_latency: u8

A read-only register that specifies how often the device needs access to the PCI bus (in 1/4 microsecond units).

Implementations§

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impl StandardDetails

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pub fn base_addrs( &self ) -> Result<[Option<BaseAddress>; 6], UnexpectedValue<u32>>

Returns this device’s base address registers (BARs).

Returns
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pub fn irq_pin(&self) -> Result<Option<IrqPin>, UnexpectedValue<u8>>

Returns which IRQ pin this device uses.

Returns

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impl Debug for StandardDetails

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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

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