Struct Idt

#[repr(C, align(16))]
pub struct Idt { /* private fields */ }

Implementations

impl Idt

pub const NUM_VECTORS: usize = 256usize

pub const DIVIDE_BY_ZERO: usize = 0usize

Divide-by-zero interrupt (#D0)

pub const DEBUG: usize = 1usize

pub const NMI: usize = 2usize

Non-maskable interrupt.

pub const BREAKPOINT: usize = 3usize

pub const OVERFLOW: usize = 4usize

pub const BOUND_RANGE_EXCEEDED: usize = 5usize

pub const INVALID_OPCODE: usize = 6usize

pub const DEVICE_NOT_AVAILABLE: usize = 7usize

A device not available exception

pub const DOUBLE_FAULT: usize = 8usize

pub const COPROCESSOR_SEGMENT_OVERRUN: usize = 9usize

On modern CPUs, this interrupt is reserved; this error fires a general protection fault instead.

pub const INVALID_TSS: usize = 10usize

pub const SEGMENT_NOT_PRESENT: usize = 11usize

pub const STACK_SEGMENT_FAULT: usize = 12usize

pub const GENERAL_PROTECTION_FAULT: usize = 13usize

pub const PAGE_FAULT: usize = 14usize

pub const X87_FPU_EXCEPTION: usize = 16usize

pub const ALIGNMENT_CHECK: usize = 17usize

pub const MACHINE_CHECK: usize = 18usize

pub const SIMD_FLOATING_POINT: usize = 19usize

pub const VIRTUALIZATION_EXCEPTION: usize = 20usize

pub const SECURITY_EXCEPTION: usize = 30usize

pub const DOUBLE_FAULT_IST_OFFSET: usize = 4usize

Chosen by fair die roll, guaranteed to be random.

pub const MAX_CPU_EXCEPTION: usize = 30usize

pub const ISA_BASE: usize = 32usize

Base offset for ISA hardware interrupts.

pub const LOCAL_APIC_TIMER: usize = 254usize

Local APIC timer interrupt vector mapped by Controller::enable_hardware_interrupts.

Systems which do not use that function to initialize the local APIC may map this interrupt to a different IDT vector.

pub const LOCAL_APIC_SPURIOUS: usize = 255usize

Local APIC spurious interrupt vector mapped by Controller::enable_hardware_interrupts.

Systems which do not use that function to initialize the local APIC may map this interrupt to a different IDT vector.

pub const PIC_BIG_START: usize = 32usize

Base of the primary PIC’s interrupt vector region mapped by Controller::enable_hardware_interrupts.

Systems which do not use that function to initialize the PICs may map this interrupt to a different IDT vector.

pub const PIC_LITTLE_START: usize = 40usize

Base of the secondary PIC’s interrupt vector region mapped by Controller::enable_hardware_interrupts.

Systems which do not use that function to initialize the PICs may map this interrupt to a different IDT vector.

pub const fn new() -> Self

pub fn register_isa_isr(&mut self, irq: IsaInterrupt, isr: *const ())

Register an interrupt service routine (ISR) for the given ISA standard PC interrupt.

pub fn register_isr(&mut self, vector: usize, isr: *const ())

pub fn load(&'static self)

pub unsafe fn load_raw(&self)

Safety

The referenced IDT must be valid for the 'static lifetime.

Trait Implementations

impl Control for Idt

type Registers = Registers

unsafe fn disable(&mut self)

Disable all interrupts.

unsafe fn enable(&mut self)

Enable all interrupts.

fn is_enabled(&self) -> bool

Returns true if interrupts are enabled.

fn register_handlers<H>(&mut self) -> Result<(), RegistrationError>

where H: Handlers<Registers>,

fn enter_critical(&mut self) -> CriticalGuard<'_, Self>

Enter a critical section, returning a guard.

impl Debug for Idt

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Idt

fn default() -> Self

Returns the “default value” for a type.